# Standard Instruction Execution Times

```
The number of clock periods shown in this table indicates the time required
to perform the operations, store the results and read the next instruction.
The number of bus read and write cycles is shown in parenthesis as (r/w).
The number of clock periods and the number of read and write cycles must be
indicated.

In the following table the headings have the following meanings:
An = address register operand, Dn = data register operand, ea = an operand
specified by an effective address, and M = memory effective address operand.

Standard Instruction Execution Times

instruction	Size		op<ea>,An ^	op<ea>,Dn	op Dn,<M>

ADD		byte,word	8(1/0) +	  4(1/0) +	 8(1/1) +
long		6(1/0) +**	  6(1/0) +**	12(1/2) +
AND		byte,word	   -		  4(1/0) +	 8(1/1) +
long		   -		  6(1/0) +**	12(1/2) +
CMP		byte,word	6(1/0) +	  4(1/0) +	   -
long		6(1/0) +	  6(1/0) +	   -
DIVS		    -		   -		158(1/0) +*	   -
DIVU		    -		   -		140(1/0) +*	   -
EOR		byte,word	   -		  4(1/0) ***	 8(1/1) +
long		   -		  8(1/0) ***	12(1/2) +
MULS		    -		   -		 70(1/0) +*	   -
MULU		    -		   -		 70(1/0) +*	   -
OR		byte,word	   -		  4(1/0) +**	 8(1/1) +
long		   -		  6(1/0) +**	12(1/2) +
SUB		byte,word	8(1/0) +	  4(1/0) +	 8(1/1) +
long		6(1/0) +**	  6(1/0) +**	12(1/2) +

^ Word or long only
* Indicates maximum value
** The base time of six clock periods is increased to eight
if the effective address mode is register direct or
*** Only available effective address mode is data register direct

DIVS,DIVU - The divide algorithm used by the MC68000 provides less
than 10% difference between the best and the worst case
timings.
MULS,MULU - The multiply algorithm requires 38+2n clocks where
n is defined as:
MULU: n = the number of ones in the <ea>
MULS: n = concatanate the <ea> with a zero as the LSB;
n is the resultant number of 10 or 01 patterns
in the 17-bit source; i.e., worst case happens
when the source is \$5555
```

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